1. Field of the Invention
The present invention relates to the field of semiconductor technology, and more particularly to a semiconductor device.
2. Description of the Related Art
By using embedded SiGe (eSiGe) processes to form source and drain regions of a PMOS (p-Channel Metal Oxide Semiconductor) device, a compressive stress can be applied to a channel region so as to increase carrier mobility of the PMOS device. Some eSiGe processes include forming a Sigma (“Σ”) shaped recess in a silicon substrate and filling the Sigma-shaped recess with bulk SiGe, which can further increase the compressive stress applied to the channel region and improve performance of the PMOS device through increased carrier mobility.
FIGS. 1A to 1D show cross-section views of a semiconductor device at different stages of fabrication using an eSiGe process in the prior art.
As shown in FIG. 1A, the semiconductor device includes a substrate 100 and gates 102 formed on a surface of the substrate 100. The semiconductor device further includes sidewalls 103 formed on side surfaces of the gates 102, and a Sigma-shaped recess 101 formed in the substrate 100 between adjacent gates 102.
As shown in FIG. 1B, a SiGe seed layer 104 is formed on a surface of the Sigma-shaped recess 101.
As shown in FIG. 1C, bulk SiGe 105 (doped with boron) is formed on a surface of the SiGe seed layer 104, with the boron-doped bulk SiGe 105 filling the Sigma-shaped recess 101. As shown in FIG. 1D, a Si cap layer 106 is formed on surfaces of the SiGe seed layer 104 and boron-doped bulk SiGe 105, and located between opposite sidewalls 103 of adjacent gates 102.
In order to achieve high carrier mobility in a PMOS device, a high concentration of Ge in the boron-doped bulk SiGe 105 may be necessary. However, a high concentration of Ge can impede boron atoms in the boron-doped bulk SiGe 105 from diffusing, which may subsequently result in portions of the SiGe seed layer 104 that are deficient in boron (see, e.g. elliptical regions 41 of FIG. 4). These boron-deficient regions can result in high external resistance, thereby impacting semiconductor device performance.
The table below shows an example of the relationship between Ge concentration (in %) and external resistance Rex (in ohms) for a particular PMOS device in the prior art.
Ge concentration18%25%Rex366 ohms3022 ohms
As shown in the above table, when the concentration of Ge increases from 18% to 25%, Rex may increase by an order of magnitude from 366 ohms to 3022 ohms. The large increase in external resistance Rex may subsequently result in degradation of semiconductor device performance.